1. Field of the Invention
The present invention relates to a system and method for supporting layout design of semiconductor integrated circuit.
2. Description of Related Art
Finer processes of a semiconductor device have advanced, and the thickness of a gate oxide film of a transistor becomes thinner so that a power supply voltage is lowered. In order to perform the adjustment of a delay variation and timing constraint due to a voltage drop (IR drop) in a power supply interconnection under a low power supply voltage, a process of the arrangement and wiring in a layout design, and a process of confirming a permissible amount of the IR drop need to be performed repeatedly, which makes the timing convergence difficult. Moreover, a malfunction might arise if a voltage drop in the entire LSI due to the IR drop is too large. Therefore, a design technique is desired which a voltage amount of an IR drop at any point (hereinafter to be referred to as an IR drop amount) is determined to a voltage at a reference point from an initial stage of design and the arrangement density restriction is performed based on the IR drop amount.
The Japanese Patent Application Publication (JP-P2007-95811A) discloses a technique as a design method based on an IR drop amount. In this method of designing a semiconductor integrated circuit, a power supply model to be analyzed is at first selected within a range of obtainable data. Next, by presupposing an initial arrangement at a chip level or lower module level of the selected power supply model, data on the tendency of the voltage drop is produced. Then, based on the produced data on the tendency of the voltage drop, an arrangement density distribution of cells and transistors is produced in accordance with the tendency of voltage trop that is estimated at an initial stage of the design of a semiconductor integrated circuit. Moreover, the produced arrangement density distribution is converted into a design data. Thus, the semiconductor integrated circuit can be designed in which the influence of the voltage drop is suppressed.
An arrangement algorithm of the arrangement tool, however, emphasizes timings at the time of the operation. Therefore, even if an arrangement constraint condition is set and the arrangement tool is performed, the cell arrangement result may not satisfy the arrangement constraint condition. Therefore, the IR drop amount is not reflected on the cell arrangement. Thus, a process of arrangement and wiring and a process of confirming a permissible amount of the IR drop are iteratively executed so as to satisfy the permissible amount of the IR drop.
Further, Japanese Patent Application Publication (JP-P2007-41774A) discloses a layout method for a basic cell. The basic cell is one of a plurality of basic cells previously prepared, and is provided with one or more logic cells. The basic cell is also provided with one or more capacitive cells between a power supply interconnection and a grand interconnection which are connected to the logic cell. A semiconductor integrated circuit is designed by combining the plurality of basic cells. The layout method for the basic cell includes a process of arranging the basic cell, a process of calculating an interconnection density, and a process of changing the basic cell, in a process of performing a layout of the basic cell. In the process of arranging the basic cell, the basic cell is arranged. In the process of calculating the interconnection density, the interconnection density is calculated from the result of the arrangement of the basic cell. In the process of changing the basic cell, the basic cell is changed to a basic cell having an input/output terminal at a different position based on the interconnection density. That is, in this method, a capacitive cell is arranged in the vicinity of the basic cell to relief of the IR drop amount, and analysis of the IR drop is performed after the logic synthesis or the layout arrangement, and then the capacitive cell is replaced with the basic cell.
Another method for designing a cell-based semiconductor integrated circuit is disclosed in Japanese Patent Application Publication (JP-P2005-142226A).